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yosys-0.56-1.20250810git8c71226.fc42 | Yosys Open SYnthesis Suite, including Verilog synthesizer | linux/x86_64![]() |
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yosys-devel-0.56-1.20250810git8c71226.fc42 | Development files to build Yosys synthesizer plugins | linux/x86_64![]() |
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yosys-doc-0.56-1.20250810git8c71226.fc42 | Documentation for Yosys synthesizer | linux/x86_64![]() |
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yosys-share-0.56-1.20250810git8c71226.fc42 | Architecture-independent Yosys files | linux/noarch![]() |
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yosyshq-abc-0.56-1.20250810gitfa7fa16.fc42 | Sequential logic synthesis and formal verification | linux/x86_64![]() |
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yosyshq-abc-devel-0.56-1.20250810gitfa7fa16.fc42 | Headers and libraries for developing with ABC | linux/x86_64![]() |
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yosyshq-abc-devel-0.56-1.20250810gitfa7fa16.fc42 | Headers and libraries for developing with ABC | linux/i686![]() | linux/x86_64![]() |
yosyshq-abc-libs-0.56-1.20250810gitfa7fa16.fc42 | Library for sequential synthesis and verification | linux/i686![]() |
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yosyshq-abc-libs-0.56-1.20250810gitfa7fa16.fc42 | Library for sequential synthesis and verification | linux/x86_64![]() | linux/i686![]() |
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Fabrice Bellet, Sun Aug 17 23:20:28 2025