benchdnn-3.6-1.1 RPM for aarch64

From OpenSuSE Ports Tumbleweed for aarch64

Intel Math Kernel Library for Deep Neural Networks (Intel MKL-DNN) is an
open-source performance library for deep-learning applications. The library
accelerates deep-learning applications and frameworks on Intel architecture.
Intel MKL-DNN contains vectorized and threaded building blocks that you can use
to implement deep neural networks (DNN) with C and C++ interfaces.

This package only includes the benchmark utility including its input files.

Provides

• benchdnn
• benchdnn(aarch-64)

Requires

• ld-linux-aarch64.so.1()(64bit)
• ld-linux-aarch64.so.1(GLIBC_2.17)(64bit)
• libc.so.6()(64bit)
• libc.so.6(GLIBC_2.17)(64bit)
• libc.so.6(GLIBC_2.32)(64bit)
• libc.so.6(GLIBC_2.34)(64bit)
• libc.so.6(GLIBC_2.38)(64bit)
• libdnnl.so.3()(64bit)
• libdnnl3 = 3.6
• libgcc_s.so.1()(64bit)
• libgcc_s.so.1(GCC_3.0)(64bit)
• libgcc_s.so.1(GCC_3.3.1)(64bit)
• libgomp.so.1()(64bit)
• libgomp.so.1(GOMP_4.0)(64bit)
• libgomp.so.1(OMP_1.0)(64bit)
• libm.so.6()(64bit)
• libm.so.6(GLIBC_2.17)(64bit)
• libm.so.6(GLIBC_2.27)(64bit)
• libm.so.6(GLIBC_2.29)(64bit)
• libstdc++.so.6()(64bit)
• libstdc++.so.6(CXXABI_1.3)(64bit)
• libstdc++.so.6(CXXABI_1.3.5)(64bit)
• libstdc++.so.6(CXXABI_1.3.8)(64bit)
• libstdc++.so.6(GLIBCXX_3.4)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.11)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.14)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.15)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.18)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.19)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.20)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.21)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.26)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.29)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.32)(64bit)
• libstdc++.so.6(GLIBCXX_3.4.9)(64bit)
• rpmlib(CompressedFileNames) <= 3.0.4-1
• rpmlib(FileDigests) <= 4.6.0-1
• rpmlib(PayloadFilesHavePrefix) <= 4.0-1
• rpmlib(PayloadIsZstd) <= 5.4.18-1

License

Apache-2.0

Changelog

* Thu Oct 17 2024 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 3.6:
    * https://github.com/oneapi-src/oneDNN/releases/tag/v3.6
* Wed Oct 02 2024 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Add openCL deps for devel package
* Tue Sep 24 2024 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Enable graph component
* Mon Sep 23 2024 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 3.5.3:
    * https://github.com/oneapi-src/oneDNN/releases/tag/v3.5.3
* Fri Apr 19 2024 Alessandro de Oliveira Faria <cabelo@opensuse.org>
  - Update to 3.4.1:
    * Fixed an issue with caching and serialization of primitives in
      deterministic mode (7ed604a)
    * Introduced memory descriptor serialization API
      (4cad420, 929a27a, 9b848c8)
    * Fixed incorrect results in fp64 convolution and deconvolution
      on Intel GPUs based on Xe-LPG architecture (ebe77b5, 0b399ac,
      d748d64, 9f4f3d5, 21a8cae)
    * Fixed incorrect results in reorder with large sizes on
      Intel CPUs and GPUs (69a111e, 4b72361, 74a343b)
    * Reduced creation time for deconvolution primitive on
      Intel CPUs (bec487e, 1eab005)
    * Fixed performance regression in deconvolution on
      Intel CPUs (fbe5b97, 1dd3c6a)
    * Removed dangling symblols from static builds
      (e92c404, 6f5621a)
    * Fixed crash during platform detection on some
      AArch64-based systems (406a079)
    * Fixed performance regression in int8 deconvolution on
      Intel CPUs (7e50e15)
    * Fixed handling of zero points for matmul in verbose
      logs converter (15c7916)
* Fri Dec 01 2023 Alessandro de Oliveira Faria <cabelo@opensuse.org>
  - Update to 3.3.3:
  - This is a patch release containing the following changes to v3.3.2:
    * Fixed performance regression in int8 convolutions on processors with Intel AVX-512 and Intel DL Boost support (a00661f)
    * Fixed race condition during library initialization on Intel Data Center GPU Max Series (7dfcd11)
    * Fixed accuracy issue in experimental Graph Compiler with LLVM code generator (8892e7e)
    * Disabled int8 RNN implementation for cases with non-trivial strides (2195e4b)
    * Fixed incorrect results in bfloat16 convolution implementation on processors with Intel AMX support (9f00af9)
    * Fixed incorrect results in fp16 and int8 convolution on Intel Core Ultra integrated GPUs (69cef84, 79bc6cc, c9c0b09)
* Fri Dec 01 2023 Alessandro de Oliveira Faria <cabelo@opensuse.org>
  - Update to 3.3.1:
  - This is a patch release containing the following changes to v3.3:
    * Fixed int8 convolution accuracy issue on Intel GPUs (09c87c7)
    * Switched internal stream to in-order mode for NVIDIA and AMD GPUs to avoid synchronization issues (db01d62)
    * Fixed runtime error for avgpool_bwd operation in Graph API (d025ef6, 9e0602a, e0dc1b3)
    * Fixed benchdnn error reporting for some Graph API cases (98dc9db)
    * Fixed accuracy issue in experimental Graph Compiler for int8 MHA variant from StarCoder model (5476ef7)
    * Fixed incorrect results for layer normalization with trivial dimensions on Intel GPUs (a2ec0a0)
    * Removed redundant synchronization for out-of-order SYCL queues (a96e9b1)
    * Fixed runtime error in experimental Graph Compiler for int8 MLP subgraph from LLAMA model (595543d)
    * Fixed SEGFAULT in experimental Graph Compiler for fp32 MLP subgraph (4207105)
    * Fixed incorrect results in experimental Graph Compiler for MLP subgraph (57e14b5)
    * Fixed the issue with f16 inner product primitive with s8 output returning unimplemented on Intel GPUs (bf12207, 800b5e9, ec7054a)
    * Fixed incorrect results for int8 deconvolution with zero-points on processors with Intel AMX instructions support (55d2cec)
* Tue Oct 10 2023 Paolo Stivanin <info@paolostivanin.com>
  - Update to 3.3:
    * 3.3: https://github.com/oneapi-src/oneDNN/releases/tag/v3.3
    * 3.2: https://github.com/oneapi-src/oneDNN/releases/tag/v3.2
    * 3.1: https://github.com/oneapi-src/oneDNN/releases/tag/v3.1
  - Drop upstreamed onednn-fix-gcc13.patch
* Tue Mar 21 2023 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 3.0.1:
    * Changes: https://github.com/oneapi-src/oneDNN/releases/tag/v3.0.1
  - Skipped 3.0:
    * Changes: https://github.com/oneapi-src/oneDNN/releases/tag/v3.0
  - Add patch to fix build with GCC13:
    * onednn-fix-gcc13.patch
  - Disable Arm Compute library support until fixed upstream
    https://github.com/oneapi-src/oneDNN/issues/1599
  - Drop upstream patches:
    * 1428.patch
    * fa93750.patch
* Tue Sep 20 2022 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Add patch to fix build with latest Arm Compute Library:
    * 1428.patch
    * fa93750.patch (dep for 1428.patch)
* Tue Sep 13 2022 Paolo Stivanin <info@paolostivanin.com>
  - Update to 2.6.2:
    * https://github.com/oneapi-src/oneDNN/releases
  - Removed onednn-1045.patch.
  - Removed onednn-xbyak-aarch64.patch.
* Tue Jun 15 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Fix build on aarch64:
    * onednn-xbyak-aarch64.patch
* Tue Jun 15 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to version 2.2.4:
    * Fixed build error with GCC 11 (eda1add)
    * Fixed an issue with reorder reporting unimplemented when
      quantizing f32 weights to s8 (4f05b76, 5d3d1e1, cc77eef)
    * Updated name for GPU gen12 architecture to xe (3d202c2)
  - Drop upstream patch:
    * 0001-common-gpu-include-thread-and-limit-headers-to-fix-G.patch
* Thu Jun 03 2021 Ferdinand Thiessen <rpm@fthiessen.de>
  - Update to version 2.2.3
    * Fixed a bug in int8 depthwise convolution ptimitive with groups
      and 1d spatial size for processors with AVX-512 and AVX2 support
    * Fixed correctness issue for PReLU primitive
    * Fixed corretness issue in reorder for blocked layouts with
      zero padding
    * Improved performance of weights reorders used by BRGEMM-based
      convolution primitive for processors with AVX-512 support
    * Added -fp-model=precise build flag for DPC++ code
    * Fixed potential memory leak in matmul primitive
    * Fixed performance of matmul primitive when fused with bias
      update and sum
    * Fixed a bug in matmul primitive when writing to non-contiguous
      destination buffer
  - Add upstream patch for GCC11 support
    * 0001-common-gpu-include-thread-and-limit-headers-to-fix-G.patch
* Thu May 27 2021 Jan Engelhardt <jengelh@inai.de>
  - Update descriptions.
* Wed May 26 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.2.2, changes:
    * Fixed performance regression in fp32 forward inner product for
    shapes with number of output channels equal to 1 for processors
    with Intel AVX-512 support (714b1fd)
    * Fixed performance regression in forward convolutions with groups
    for processors with Intel AVX-512 support(3555d4a)
    * Removed -std=c++11 build flag for DPC++ headers (1fcb867)
    * Fixed buffer access in initializing workspace in RNN
    implementation on GPU (9b03091)
    * Fixed fix a bug in convolution with 1x1 kernel and mixed
    strides on processors with Intel AVX-512 support (d0b3e3f)
    * Used getauxval for Linux to get CPU features on for AArch64
    systems (25c4cea)
    * Added -fp-model=precise build flag for DPC++ code (3e40e5e)
    * Fixed out-of-bounds writes in elementwise primitive on
    Intel Processor Graphics (bcf823c)
  - Fix build with Arm Compute Library:
    * onednn-1045.patch
* Tue Apr 13 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.2.1, changes:
    * From 2.2:
    Fixed segfault for cases when primitive descriptor or attributed contain NaN (e6d05ec, dbca1e9, 0326b09, 0326b09)
    Fixed engine creation failure for GPU subdevices (4c3a114)
    Fixed long lines clipping in verbose output (70d70a8)
    Fixed segfault in bfloat16 convolution weight gradient implementation on processors with Intel AMX support (a3a73a3)
    Fixed performance regression in binary primitive with per_oc broadcast strategy (9ac85d8)
    Worked around a bug with Microsoft Visual C++ compiler version detection in CMake 3.19 (2f39155)
    Removed -std=c++11 build flag for DPC++ code to align with SYCL standard (1b026f5)
    * Changes between 2.1 and 2.2:
    Performance Optimizations
      Intel Architecture processors
      Improved performance of int8 compute functionality for future Intel Xeon Scalable processor (code name Sapphire Rapids). The functionality is disabled by default and should be enabled via CPU dispatcher control.
      Improved performance of compute functionality for future Intel Core processor with Intel AVX2 and Intel DL Boost instructions support (code name Alder Lake).
      Improved fp32 inner product forward propagation performance for processors with Intel AVX-512 support.
      Improved dnnl_gemm performance for cases with n=1 on all supported processors.
      Intel Graphics products
      Introduced NHWC format support for activations for int8 primitives.
      AArch64-based processors
      Improved performance of fp32 and int8 convolution, and softmax primitives for processors with SVE 512 support.
      Improved performance of fp32 convolution via Arm Compute Library (ACL).
      Improved performance of convolution with a combination of sum and relu post-ops via ACL.
    Functionality
      Extended eltwise primitive with support for mish and hardswish algorithms.
      Extended binary primitive with support for comparison operators.
      Introduced support for post-ops in GPU resampling implementation.
      Introduced asymmetric quantization support for int8 deconvolution.
      Introduced binary post-ops support for matmul primitive.
    Usability
      Improved presentation of oneDNN primitives in VTune Amplifier.
      Introduced Linux perf support for AArch64.
      Introduced support for Fujitsu C++ compiler.
      Introduced a build time check for minimal supported ACL version. Currently oneDNN requires ACL 21.02 or later.
      Added support for cuDNN 8.x
* Wed Feb 17 2021 Guillaume GARDET <guillaume.gardet@opensuse.org>
  - Update to 2.1
  - Add Arm ComputeLibrary support on aarch64

Files

/usr/bin/benchdnn
/usr/share/benchdnn
/usr/share/benchdnn/inputs
/usr/share/benchdnn/inputs/binary
/usr/share/benchdnn/inputs/binary/harness_binary_bf16
/usr/share/benchdnn/inputs/binary/harness_binary_different_dt
/usr/share/benchdnn/inputs/binary/harness_binary_f16
/usr/share/benchdnn/inputs/binary/harness_binary_f32
/usr/share/benchdnn/inputs/binary/harness_binary_i8
/usr/share/benchdnn/inputs/binary/harness_binary_regression
/usr/share/benchdnn/inputs/binary/option_set_all
/usr/share/benchdnn/inputs/binary/option_set_fwks_ext_gpu
/usr/share/benchdnn/inputs/binary/option_set_fwks_key_gpu
/usr/share/benchdnn/inputs/binary/option_set_minimal
/usr/share/benchdnn/inputs/binary/option_set_src0_bcast
/usr/share/benchdnn/inputs/binary/perf_binary_gpu
/usr/share/benchdnn/inputs/binary/shapes_ci
/usr/share/benchdnn/inputs/binary/shapes_perf_1st_conv
/usr/share/benchdnn/inputs/binary/shapes_perf_scaleshift
/usr/share/benchdnn/inputs/binary/test_binary_all
/usr/share/benchdnn/inputs/binary/test_binary_bfloat16
/usr/share/benchdnn/inputs/binary/test_binary_ci
/usr/share/benchdnn/inputs/binary/test_binary_different_dt_ci
/usr/share/benchdnn/inputs/binary/test_binary_float16
/usr/share/benchdnn/inputs/binary/test_binary_gpu
/usr/share/benchdnn/inputs/binary/test_binary_smoke
/usr/share/benchdnn/inputs/bnorm
/usr/share/benchdnn/inputs/bnorm/option_set_fwks_ext_gpu
/usr/share/benchdnn/inputs/bnorm/option_set_fwks_key_gpu
/usr/share/benchdnn/inputs/bnorm/perf_bnorm_gpu
/usr/share/benchdnn/inputs/bnorm/set_nd
/usr/share/benchdnn/inputs/bnorm/shapes_1d
/usr/share/benchdnn/inputs/bnorm/shapes_2d
/usr/share/benchdnn/inputs/bnorm/shapes_3d
/usr/share/benchdnn/inputs/bnorm/shapes_ci
/usr/share/benchdnn/inputs/bnorm/shapes_densenet_121
/usr/share/benchdnn/inputs/bnorm/shapes_googlenet_v2
/usr/share/benchdnn/inputs/bnorm/shapes_googlenet_v3
/usr/share/benchdnn/inputs/bnorm/shapes_large
/usr/share/benchdnn/inputs/bnorm/shapes_regressions
/usr/share/benchdnn/inputs/bnorm/shapes_resnet_50
/usr/share/benchdnn/inputs/bnorm/shapes_topologies_small
/usr/share/benchdnn/inputs/bnorm/test_bnorm_all_blocked
/usr/share/benchdnn/inputs/bnorm/test_bnorm_all_plain
/usr/share/benchdnn/inputs/bnorm/test_bnorm_bfloat16_blocked
/usr/share/benchdnn/inputs/bnorm/test_bnorm_bfloat16_plain
/usr/share/benchdnn/inputs/bnorm/test_bnorm_ci
/usr/share/benchdnn/inputs/bnorm/test_bnorm_float16_plain
/usr/share/benchdnn/inputs/bnorm/test_bnorm_gpu
/usr/share/benchdnn/inputs/bnorm/test_bnorm_regressions
/usr/share/benchdnn/inputs/bnorm/test_bnorm_regressions_large
/usr/share/benchdnn/inputs/bnorm/test_bnorm_smoke
/usr/share/benchdnn/inputs/brgemm
/usr/share/benchdnn/inputs/brgemm/harness_brgemm_f32
/usr/share/benchdnn/inputs/brgemm/harness_brgemm_f8
/usr/share/benchdnn/inputs/brgemm/harness_brgemm_fpmath
/usr/share/benchdnn/inputs/brgemm/option_set_bf16
/usr/share/benchdnn/inputs/brgemm/option_set_f32
/usr/share/benchdnn/inputs/brgemm/option_set_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_tail_n_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_tail_n_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_big_k_tail_n_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_no_tail_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_no_tail_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_no_tail_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_tail_n_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_tail_n_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_k_tail_n_int8
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_n_bf16
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_n_f32
/usr/share/benchdnn/inputs/brgemm/shapes_2d_tail_n_int8
/usr/share/benchdnn/inputs/brgemm/test_brgemm_all
/usr/share/benchdnn/inputs/brgemm/test_brgemm_bf16
/usr/share/benchdnn/inputs/brgemm/test_brgemm_ci
/usr/share/benchdnn/inputs/brgemm/test_brgemm_f16
/usr/share/benchdnn/inputs/brgemm/test_brgemm_f32
/usr/share/benchdnn/inputs/brgemm/test_brgemm_f8
/usr/share/benchdnn/inputs/brgemm/test_brgemm_int8
/usr/share/benchdnn/inputs/brgemm/test_brgemm_smoke
/usr/share/benchdnn/inputs/concat
/usr/share/benchdnn/inputs/concat/option_set_fwks_ext_gpu
/usr/share/benchdnn/inputs/concat/option_set_fwks_key_gpu
/usr/share/benchdnn/inputs/concat/option_set_gen9_gpu
/usr/share/benchdnn/inputs/concat/test_concat_all
/usr/share/benchdnn/inputs/concat/test_concat_bfloat16
/usr/share/benchdnn/inputs/concat/test_concat_ci
/usr/share/benchdnn/inputs/concat/test_concat_float16
/usr/share/benchdnn/inputs/concat/test_concat_gpu
/usr/share/benchdnn/inputs/concat/test_concat_smoke
/usr/share/benchdnn/inputs/conv
/usr/share/benchdnn/inputs/conv/harness_conv_arbitrary_dst
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_gpu
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_int8
/usr/share/benchdnn/inputs/conv/harness_conv_attrs_int8_asymmetric
/usr/share/benchdnn/inputs/conv/harness_conv_auto
/usr/share/benchdnn/inputs/conv/harness_conv_deepbench
/usr/share/benchdnn/inputs/conv/harness_conv_depthwise_int8
/usr/share/benchdnn/inputs/conv/harness_conv_dilated_3d
/usr/share/benchdnn/inputs/conv/harness_conv_dilated_int8
/usr/share/benchdnn/inputs/conv/harness_conv_dw_bfloat16
/usr/share/benchdnn/inputs/conv/harness_conv_dw_bfloat16_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_dw_float16_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_dw_fp8_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_f32
/usr/share/benchdnn/inputs/conv/harness_conv_f32_nxc
/usr/share/benchdnn/inputs/conv/harness_conv_fused_depthwise
/usr/share/benchdnn/inputs/conv/harness_conv_int8
/usr/share/benchdnn/inputs/conv/harness_conv_regression_general
/usr/share/benchdnn/inputs/conv/harness_conv_saturation_int8
/usr/share/benchdnn/inputs/conv/harness_conv_tags
/usr/share/benchdnn/inputs/conv/harness_conv_zero_points
/usr/share/benchdnn/inputs/conv/option_set_all_eltwise_postops
/usr/share/benchdnn/inputs/conv/option_set_combined_postops
/usr/share/benchdnn/inputs/conv/option_set_fwks_ext_gpu
/usr/share/benchdnn/inputs/conv/option_set_fwks_key_gpu
/usr/share/benchdnn/inputs/conv/perf_conv_bdw_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_clx_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_gen9
/usr/share/benchdnn/inputs/conv/perf_conv_skx_1sock
/usr/share/benchdnn/inputs/conv/perf_conv_xe_hp
/usr/share/benchdnn/inputs/conv/perf_conv_xe_lp
/usr/share/benchdnn/inputs/conv/set_all_topologies
/usr/share/benchdnn/inputs/conv/set_conv_3d
/usr/share/benchdnn/inputs/conv/set_conv_all
/usr/share/benchdnn/inputs/conv/set_conv_dw
/usr/share/benchdnn/inputs/conv/set_dilated-conv
/usr/share/benchdnn/inputs/conv/set_dilated-conv_1st
/usr/share/benchdnn/inputs/conv/set_dilated-conv_3d
/usr/share/benchdnn/inputs/conv/set_fastrcnn
/usr/share/benchdnn/inputs/conv/set_gpu
/usr/share/benchdnn/inputs/conv/set_maskrcnn
/usr/share/benchdnn/inputs/conv/set_perf_cpu_all_mb
/usr/share/benchdnn/inputs/conv/set_perf_cpu_inference_only
/usr/share/benchdnn/inputs/conv/set_perf_cpu_large_mb
/usr/share/benchdnn/inputs/conv/set_perf_cpu_small_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_all_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_large_mb
/usr/share/benchdnn/inputs/conv/set_perf_gpu_small_mb
/usr/share/benchdnn/inputs/conv/set_topologies_inference_only
/usr/share/benchdnn/inputs/conv/shapes_1d
/usr/share/benchdnn/inputs/conv/shapes_1d_wavenet
/usr/share/benchdnn/inputs/conv/shapes_1x1
/usr/share/benchdnn/inputs/conv/shapes_3d
/usr/share/benchdnn/inputs/conv/shapes_3d_1st_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_1x1_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_2d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_gpu
/usr/share/benchdnn/inputs/conv/shapes_3d_i3d
/usr/share/benchdnn/inputs/conv/shapes_3d_resnext101
/usr/share/benchdnn/inputs/conv/shapes_3d_strided_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_strided_padding
/usr/share/benchdnn/inputs/conv/shapes_3d_unet
/usr/share/benchdnn/inputs/conv/shapes_3d_unit-stride_no-padding
/usr/share/benchdnn/inputs/conv/shapes_3d_unit-stride_padding
/usr/share/benchdnn/inputs/conv/shapes_a3c
/usr/share/benchdnn/inputs/conv/shapes_alexnet
/usr/share/benchdnn/inputs/conv/shapes_auto
/usr/share/benchdnn/inputs/conv/shapes_basic
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Fabrice Bellet, Fri Jan 24 23:52:04 2025