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Alliance is a complete set of free cad tools and portable libraries for VLSI design. It includes a vhdl compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable cmos libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors ieee Gigabit HSL Router. Alliance provides CAD tools covering most of all the digital design flow: * VHDL Compilation and Simulation * Model checking and formal proof * RTL and Logic synthesis * Data-Path compilation * Macro-cells generation * Place and route * Layout edition * Netlist extraction and verification * Design rules checking Alliance is listed among Fedora Electronic Lab (FEL) packages.
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