EPEL 8 for s390x : / usr /share /uhd /images

• LICENSE
• bit
• inventory.json
• octoclock_bootloader.hex
• octoclock_r4_fw.hex
• usrp1_fpga.rbf
• usrp1_fpga_4rx.rbf
• usrp1_fw.ihx
• usrp2_fpga.bin
• usrp2_fw.bin
• usrp_b100_fpga.bin
• usrp_b100_fpga_2rx.bin
• usrp_b100_fw.ihx
• usrp_b200_bl.img
• usrp_b200_fpga.bin
• usrp_b200_fw.hex
• usrp_b200mini_fpga.bin
• usrp_b205mini_fpga.bin
• usrp_b210_fpga.bin
• usrp_e310_fpga.bin
• usrp_e310_fpga.bit
• usrp_e310_fpga.rpt
• usrp_e310_fpga_sg3.bin
• usrp_e310_fpga_sg3.bit
• usrp_e310_fpga_sg3.rpt
• usrp_e320_fpga_1G.bit
• usrp_e320_fpga_1G.bit.md5
• usrp_e320_fpga_1G.dts
• usrp_e320_fpga_1G.dts.md5
• usrp_e320_fpga_1G.rpt
• usrp_e320_fpga_AA.bit
• usrp_e320_fpga_AA.bit.md5
• usrp_e320_fpga_AA.dts
• usrp_e320_fpga_AA.dts.md5
• usrp_e320_fpga_AA.rpt
• usrp_e320_fpga_XG.bit
• usrp_e320_fpga_XG.bit.md5
• usrp_e320_fpga_XG.dts
• usrp_e320_fpga_XG.dts.md5
• usrp_e320_fpga_XG.rpt
• usrp_e3xx_fpga_idle.bin
• usrp_e3xx_fpga_idle.bit
• usrp_e3xx_fpga_idle.rpt
• usrp_e3xx_fpga_idle_sg3.bin
• usrp_e3xx_fpga_idle_sg3.bit
• usrp_e3xx_fpga_idle_sg3.rpt
• usrp_n200_fw.bin
• usrp_n200_r2_fpga.bin
• usrp_n200_r3_fpga.bin
• usrp_n200_r4_fpga.bin
• usrp_n210_fw.bin
• usrp_n210_r2_fpga.bin
• usrp_n210_r3_fpga.bin
• usrp_n210_r4_fpga.bin
• usrp_n230_fpga.bin
• usrp_n230_fpga.bit
• usrp_n230_fpga.rpt
• usrp_n300_fpga_AA.bit
• usrp_n300_fpga_AA.bit.md5
• usrp_n300_fpga_AA.dts
• usrp_n300_fpga_AA.dts.md5
• usrp_n300_fpga_AA.rpt
• usrp_n300_fpga_HG.bit
• usrp_n300_fpga_HG.bit.md5
• usrp_n300_fpga_HG.dts
• usrp_n300_fpga_HG.dts.md5
• usrp_n300_fpga_HG.rpt
• usrp_n300_fpga_WX.bit
• usrp_n300_fpga_WX.bit.md5
• usrp_n300_fpga_WX.dts
• usrp_n300_fpga_WX.dts.md5
• usrp_n300_fpga_WX.rpt
• usrp_n300_fpga_XG.bit
• usrp_n300_fpga_XG.bit.md5
• usrp_n300_fpga_XG.dts
• usrp_n300_fpga_XG.dts.md5
• usrp_n300_fpga_XG.rpt
• usrp_n310_fpga_AA.bit
• usrp_n310_fpga_AA.bit.md5
• usrp_n310_fpga_AA.dts
• usrp_n310_fpga_AA.dts.md5
• usrp_n310_fpga_AA.rpt
• usrp_n310_fpga_HG.bit
• usrp_n310_fpga_HG.bit.md5
• usrp_n310_fpga_HG.dts
• usrp_n310_fpga_HG.dts.md5
• usrp_n310_fpga_HG.rpt
• usrp_n310_fpga_WX.bit
• usrp_n310_fpga_WX.bit.md5
• usrp_n310_fpga_WX.dts
• usrp_n310_fpga_WX.dts.md5
• usrp_n310_fpga_WX.rpt
• usrp_n310_fpga_XG.bit
• usrp_n310_fpga_XG.bit.md5
• usrp_n310_fpga_XG.dts
• usrp_n310_fpga_XG.dts.md5
• usrp_n310_fpga_XG.rpt
• usrp_n320_fpga_AQ.bit
• usrp_n320_fpga_AQ.bit.md5
• usrp_n320_fpga_AQ.dts
• usrp_n320_fpga_AQ.dts.md5
• usrp_n320_fpga_AQ.rpt
• usrp_n320_fpga_HG.bit
• usrp_n320_fpga_HG.bit.md5
• usrp_n320_fpga_HG.dts
• usrp_n320_fpga_HG.dts.md5
• usrp_n320_fpga_HG.rpt
• usrp_n320_fpga_WX.bit
• usrp_n320_fpga_WX.bit.md5
• usrp_n320_fpga_WX.dts
• usrp_n320_fpga_WX.dts.md5
• usrp_n320_fpga_WX.rpt
• usrp_n320_fpga_XG.bit
• usrp_n320_fpga_XG.bit.md5
• usrp_n320_fpga_XG.dts
• usrp_n320_fpga_XG.dts.md5
• usrp_n320_fpga_XG.rpt
• usrp_n320_fpga_XQ.bit
• usrp_n320_fpga_XQ.bit.md5
• usrp_n320_fpga_XQ.dts
• usrp_n320_fpga_XQ.dts.md5
• usrp_n320_fpga_XQ.rpt
• usrp_x300_fpga_HG.bit
• usrp_x300_fpga_HG.lvbitx
• usrp_x300_fpga_HG.rpt
• usrp_x300_fpga_XG.bit
• usrp_x300_fpga_XG.lvbitx
• usrp_x300_fpga_XG.rpt
• usrp_x310_fpga_HG.bit
• usrp_x310_fpga_HG.lvbitx
• usrp_x310_fpga_HG.rpt
• usrp_x310_fpga_XG.bit
• usrp_x310_fpga_XG.lvbitx
• usrp_x310_fpga_XG.rpt

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Fabrice Bellet, Thu Mar 27 03:02:23 2025